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Features
* * * * * * * * * * * * *
Programmable Driver Current Regulation Antenna Driver Stage for 1 A Peak Current LF Baudrates between 1 kbaud to 8 kbaud Integrated Oscillator for Ceramic Resonators Two Inputs for Push-button Switches Bi-directional Single-wire Interface Diagnosis Function and Overtemperature Protection Quick Start Control (QSC) for Fast Oscillation Build-up and Decay Timing Operation Temperature -40C to +85C Carrier Frequency Range from 100 kHz to 150 kHz Amplitude Shift Keying (ASK) Modulation Phase Shift Keying (PSK) Modulation Power Supply Range 7 V to 16 V Direct Battery Input (6 V and 28 V with Limited Function Range) * EMI and ESD According to Automotive Requirements * Highly Integrated -- Less External Components Required
Stand-alone Antenna Driver ATA5277 Preliminary
Applications
* Car Access
Benefits
* Dedicated for Decentralized Systems * Constant Magnetic Field Strength Electrostatic sensitive device. Observe precautions for handling.
Description
The circuit is an integrated BCDMOS antenna driver IC dedicated as a transmitter for Passive Entry/Go (PEG) car applications and for other handsfree access control applications. It includes the full functionality to generate a magnetic LF field in conjunction with an antenna coil to transmit data to a receiver in a key fob, card or transponder. The transmission can be controlled via an one wire I/O interface (DIO) by an external control unit.
Rev. 4669B-RKE-10/03
Figure 1. Block Diagram
VL1 VL2 VL3 CINT VBATT VDD OSCI OSCO VSW
PGND1 PGND2 PGND3 VDS CBOOST DRV1
Boost converter control
5V Regulator
Switch Oscillator debounce and wake-up
SW1
ATA5277
HS driver LS driver Driver control logic Control and status register
SW2
CLKO
VDIO QSC
Current and zero crossing sensing Serial interface (single wire )
DIO
VSHUNT
AGND
DGND TEST SCANE SCANI
Pin Configuration
Figure 2. Pinning QFN 28
PGND1 PGND2 PGND3 VDS DRV1 CBOOST NC
1 2 3 4 5 6 7
28 27 26 25 24 23 22 21 20 19 ATA5277 18 17 16 15 8 9 10 11 12 13 14 QSC VSHUNT AGND DGND CINT VDIO DIO
VL3 VL2 VL1 SCANE VBATT SW2 VSW SW1 VDD OSCI OSCO CLKO TEST SCANI
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ATA5277 [Preliminary]
Pin Description
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Symbol PGND1 PGND2 PGND3 VDS DRV1 CBOOST NC QSC VSHUNT AGND DGND CINT VDIO DIO SCANI TEST CLKO OSCO OSCI VDD SW1 VSW SW2 VBATT SCANE VL1 VL2 VL3 Function Power supply ground Power supply ground Power supply ground Driver voltage supply input Antenna driver stage output External bootstrap capacitor connection Not connected QSC transistor driver stage output Antenna current sensing Analog ground (sensoric and antenna driver) Digital ground (logic) External integrator capacitor connection DIO line interface supply voltage One-wire serial interface line For test purposes only For test purposes only Clock output Oscillator output (for resonator/crystal connection) Oscillator input (for external source or resonator/crystal) 5 V supply output (for filter capacitor only) Door switch input 1 Door switch interface supply voltage Door switch input 2 Battery supply voltage 7 V to 16 V (28 V jump start) For test purposes only Coil input of the switch mode power supply Coil input of the switch mode power supply Coil input of the switch mode power supply
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Functional Description
General Description
The IC contains a half-bridge coil driver stage with a special driver voltage regulator and control logic with diagnosis circuitry. Further it contains a one-wire bi-directional microcontroller interface for the carrier modulation and the mode selection. An integrated oscillator for ceramic resonators generates the clock signal for the control logic. Additionally, the IC contains two connectors for switches to wake-up the IC. The IC generates an electromagnetic LF field in combination with an LC antenna circuitry. The carrier frequency for the antenna is generated by the oscillator and prescaler logic. The LF field can be modulated to transmit data to a suitable receiver. There are two modulation modes available, Amplitude Shift Keying (ASK) and 180 Phase Shift Keying (PSK). A microcontroller or another control unit must be used to control the transmitter via the bi-directional single-wire interface. A boost converter power supply is used to supply the driver half-bridge and the antenna with a high voltage and a regulated current even if the battery voltage is low. The antenna current is programmable in 16 steps to support a transmission with various field strengths. The driver circuitry is Short Circuit (SC) protected and the driver logic contains diagnosis functions for short circuit and open wire detection at the antenna outputs.
Operation Modes
Three different operation modes are defined: * * * Standby Command mode Modulation mode
After power-on reset, the ATA5277 is in standby mode. To achieve minimum power consumption, only the internal 5-V supply, the DIO-line interface and the door switch inputs are active. The IC can be activated either by the external control unit via the serial interface or by one of the switch inputs. A low signal at the DIO-line or at the switch inputs (SW1, SW2) powers up the IC. If this is done at a switch input, a low signal is generated on the DIO-line which can be used as a wake-up signal for the connected microcontroller. In command mode, the IC can be configured and diagnostics can be run. This mode is always activated after wake-up from standby mode and after leaving modulation mode. The communication is based on a one-wire serial interface (DIO-line) with the connected microcontroller being the master and ATA5277 being the slave. In this mode, the antenna driver stage is disabled, except if the automatic field generation after wake-up is selected. In modulation mode, the antenna driver stage is activated (if enabled) and the data applied to the DIO-line modulates the LF field (in ASK or PSK). This mode is activated after the command mode and remains active as long as data is applied to the DIO-line (i.e., until a timeout has occured). After that, the IC falls back to command mode.
Standby and Wake-up
There are two different wake-up modes. In the default mode the antenna driver stage remains off after wake-up. The second mode can be programmed by a control command. Here, also the driver output stage is enabled. The IC generates the carrier signal for the antenna immediately.
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ATA5277 [Preliminary]
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ATA5277 [Preliminary]
Figure 3. Wake-up by External Switch
Ext. switch DIO line Carrier state t deb t wake
In Figure 3, the IC is woken up by an external switch (pulled to ground). After a debouncing time tdeb, the IC leaves sleep mode and sends a wake-up impulse to a connected microcontroller via the DIO line. Note that this impulse is already the start bit of the first command. After that, the ATA5277 waits for a control or status command from the microcontroller. The carrier remains off as the configuration bit M_Wake (see control command 2) is '0'. Figure 4. Wake-up by External Switch, Automatic Field Generation
Ext. switch DIO line Carrier state t deb t wake
The wake-up event as shown in Figure 4 is the same as in Figure 3, except for the configuration bit M_Wake which is '1'. The driver stage will start operation after the wake-up command has been confirmed. This behaviour can be used to build up an LF field independently of the connected microcontroller. Figure 5. Wake-up by Connected Microcontroller, Automatic Field Generation
Ext. switch DIO line Carrier state t deb t wake
Figure 5 shows a wake-up event triggered by the connected microcontroller, which now pulls the DIO line to ground. To prevent the ATA5277 from waking up due to noise on the DIO line, there is also a debouncing time before it will start operation. In this example, M_Wake is again '1', so the driver stage starts operation after the wake-up event has been confirmed.
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There are two ways to enter standby mode. One is to keep the DIO-line at a high level for more than 32 ms while the IC is in command mode. A low signal at the DIO line keeps the IC active and resets the standby timer. As the clock output CLKO remains active, this configuration can be used to supply a clock signal to a connected microcontroller. The second way to shut down the ATA5277 is to set the STBY bit to control command 0. Note that the IC will switch off operation immediately after receiving the last data bit (bit 3) of the control command. The rest of the telegram (i.e., acknowledge and stop bit) is then omitted.
Command Mode Protocol
As described above, the communication between a controlling unit and the ATA5277 is done via a one-wire serial interface. Figure 6 shows the structure of one communication bit. Figure 6. Structure of One Communication Bit
Valid data
t sync tsetup tdata tbit t recover
All bits start with a falling edge. This pull-down has to be done by the microcontroller and maintained for at least tsync,minimum. After that, the setup for the data bit itself has to be performed. If the ATA5277 is the receiver, the microcontroller has to change the state of the DIO-line according to the bit it wants to transmit. The maximum time for this setup is tsetup,maximum. This state should then be applied for a time of at least tdata,minimum. Independent of the former state of the DIO-line, it has to return to '1' and keep this state for a minimum time of trecover,minimum. If the ATA5277 is the transmitter of the data, the IC will apply the bit to the DIO-line after tsync,minimum (i.e., activate the internal pull-down when a '0' needs to be transmitted). This signal on the DIO-line is then valid for tdata,maximum. Generally, the following conditions have to be met in all cases: * * * * * tsync,minimum tsync < tsetup,maximum tsetup tsetup,maximum tdata tdata,maximum trecover trecover,minimum tbit tbit,minimum
The timing values can be found in the electrical characteristics section for the DIO interface. A command consists of a start bit followed by four command bits and four control or status bits respectively. It ends with an acknowledge bit and, if no further commands are to be transmitted, a stop bit.
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ATA5277 [Preliminary]
Any command is preceded by a start bit. Note again that, if the ATA5277 is woken up by one of the external switches, the wake-up signal from the ATA5277 (slave) to the microcontroller (master) on the DIO-line is already the start bit of the first command. It is followed by the command bits CMD0...CMD3. Bits CMD0 to CMD2 are used to select one of the eight registers of control and status bits. These registers have a depth of four bits and are used to configure the ATA5277 and to check its status. The CMD3 bit is used to select the operation mode of the ATA5277 after the current command has been processed (i.e., switch to modulation mode or stay in command mode). The next four bits of the protocol (Bit0 to Bit3) are the data bits. Depending on the selected register, these bits are to be transmitted by the microcontroller (for control commands) or by ATA5277 (for status commands). Note that even if data is transmitted by ATA5277, the initial falling edge for any bit has to be transmitted by the microcontroller, as it is the master of the transmission. Furthermore, the IC has a built-in bit error check for input bits. If no errors are detected during a command transfer, the IC acknowledges the command with N_ACKN = 0. If a bit error is detected, the transfer is not acknowledged (N_ACKN =1), the received data is dismissed and the command has to be sent again immediately. Figure 7. Data Consistency Check
As can be seen in Figure 7, the state of the DIO line is sampled twice during the datavalid time. During this time, the state must not change, both samples must result in the same value. If they differ, the N_ACKN bit is set to '1' and thus a fault is reported at the end of the sequence. The bit is reset after each control/status command (i.e., after it is transmitted to the microcontroller). If the controller receives a '1' acknowledge bit, it has to repeat the command immediately (i.e., without transmitting the stop bit), starting again with the start bit. The stop bit is used to end the command mode. After receiving the stop bit, the IC switches to modulation mode. Note that this bit is omitted if the CMD3 bit has been sent as a '1' (i.e., another command is to be transmitted). Figure 8. Control/Status Command Structure
Command Bits Standby or Command Mode Start CMD0 CMD1 CMD2 CMD3 Bit 0 Control and Status Bits Bit 1 Bit 2 Bit 3 N_Ackn Stop Modulation Mode
Sample point 1
Sample point 2
DIO
Wake-up IN IN IN IN IN/OUT IN/OUT IN/OUT IN/OUT OUT
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Figure 8 shows a typical sequence for data communication with the ATA5277. Any status/command sequence is started with a start bit. The shown sequence requires the CMD3 bit to be '0', as the protocol ends with the stop bit and after that, modulation mode is activated. If another command should be transmitted, the CMD3 bit of the preceding command must be '1' and the new command, which starts again with a start bit, is applied right after the acknowledge bit of the preceding command. Usually, the driver output stage is disabled during command mode. But as described above, by setting the M_Wake bit to '1', the driver stage will be enabled together with the command mode after wake-up. Note that this is only happening after a wake-up from standby mode. The driver stage will be disabled when switching back from modulation mode to command mode, even with the M_Wake bit set to '1'. If the DIO-line is kept in a passive state (i.e., '1') for more than 32 ms, the IC will fall into sleep mode.
Command Tables
Table 1. Control Command 0
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Note: Name/Value 0 0 0 X C_ON STBY NASK_PSK TMOD_SEL
The following tables contain the description of the eight ATA5277 commands.
Type Cmd bit Cmd bit Cmd bit Cmd bit Ctrl bit Ctrl bit Ctrl bit Ctrl bit
Function 1 Command selection Command selection Command selection
Function 2 - - -
'0' Return to modulation mode '0' Carrier/driver off '0' No effect(1) '0' ASK modulation mode
(1) (1) (1)
'1' Keep command mode '1' Carrier/driver on '1' Invokes standby mode '1' PSK modulation mode '1' Modulation timeout 500 s
'0' Modulation timeout 2 ms
1. Default values after power-on reset
Table 2. Control Command 1
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Note: Name/Value 1 0 0 X I_coil0 I_coil1 I_coil2 I_coil3 Type Cmd bit Cmd bit Cmd bit Cmd bit Ctrl bit Ctrl bit Ctrl bit Ctrl bit Function 1 Command selection Command selection Command selection Function 2 - - -
'0' Return to modulation mode
Bit0 of the current control stage
(1)
'1' Keep command mode
- - - -
Bit1 of the current control stage(1) Bit2 of the current control stage Bit3 of the current control stage
(1) (1)
1. See coil current adjustment, default all bits '1'
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ATA5277 [Preliminary]
Table 3. Control Command 2
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Note: Name/Value 0 1 0 X PS_CLK M_Wake DIS_SW1 DIS_sw2 Type Cmd bit Cmd bit Cmd bit Cmd bit Ctrl bit Ctrl bit Ctrl bit Ctrl bit Function 1 Command selection Command selection Command selection Function 2 - - -
'0' Return to modulation mode '0' Disable prescaler for CLKO-pin '0' Carrier off after wake-up(1) '0' SW1 input pull-up on(1) '0' SW2 input pull-up on
(1)
'1' Keep command mode '1' Enable prescaler (/2) for CLKO-pin(1) '1' Carrier on after wake-up '1' SW1 input pull-up off '1' SW2 input pull-up off
1. Default values after power on reset
Table 4. Status Command 3
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Name/Value 1 1 0 X SW1 SW2 - - Type Cmd bit Cmd bit Cmd bit Cmd bit Status bit Status bit - - Function 1 Command selection Command selection Command selection Function 2 - - -
'0' Return to modulation mode
Logical level at SW1 input (low: 0; high: 1) Logical level at SW2 input (low: 0; high: 1) Not used Not used
'1' Keep command mode
- - - -
Table 5. Status Command 4
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Name/Value 0 0 1 X DIAG0 DIAG1 DIAG2 - Type Cmd bit Cmd bit Cmd bit Cmd bit Status bit Status bit Status bit - Function 1 Command selection Command selection Command selection Function 2 - - -
'0' Return to modulation mode
Diagnosis bit0 Diagnosis bit0 Diagnosis bit0 Not used
'1' Keep command mode
- - - -
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Table 6. Status Command 5
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Name/Value 1 0 1 X C_ON STBY NASK_PSK TMOD_SEL Type Cmd bit Cmd bit Cmd bit Cmd bit Status bit Status bit Status bit Status bit Function 1 Command selection Command selection Command selection Function 2 - - -
'0' return to modulation mode '0' carrier/driver off '0' '0' ASK modulation selected '0' modulation timeout is 2 ms
'1' Keep command mode '1' Carrier/driver on
-
'1' PSK modulation selected '1' Modulation timeout is 500 s
Table 7. Status Command 6
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Name/Value 0 1 1 X I_coil0 I_coil1 I_coil2 I_coil3 Type Cmd bit Cmd bit Cmd bit Cmd bit Status bit Status bit Status bit Status bit Function 1 Command selection Command selection Command selection Function 2 - - -
'0' Return to modulation mode
Bit0 of the current control stage Bit1 of the current control stage Bit2 of the current control stage Bit3 of the current control stage
'1' Keep command mode
- - - -
Table 8. Status Command 7
Bit CMD0 CMD1 CMD2 CMD3 Bit0 Bit1 Bit2 Bit3 Name/Value 1 1 1 X PS_CLK M_Wake DIS_SW1 DIS_SW2 Type Cmd bit Cmd bit Cmd bit Cmd bit Status bit Status bit Status bit Status bit Function 1 Command selection Command selection Command selection Function 2 - - -
'0' return to modulation mode '0' prescaler for CLKO-pin disabled '0' carrier off after wake-up '0' SW1 input pull-up on '0' SW2 input pull-up on
'1' keep command mode '1' prescaler (/2) for CLKO pin enabled '1' carrier onafter wake-up '1' SW1 input pull-up off '1' SW2 input pull-up off
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ATA5277 [Preliminary]
Modulation
After the IC has woken up and a command has been received, the DIO line is used for LF modulation. The IC has two modulation modes, ASK and PSK. The mode can be selected with the control command '0', bit 2. If ASK modulation mode is selected (NASK_PSK = 0), the IC switches the carrier on and off, depending on the state of the DIO line ('1' is on, '0' is off). Note that, depending on the quality of the connected LF antenna and on the desired LF data rate, the usage of the QSC transistor T1 (see typical applications section) is neccessary. If PSK mode is selected (NASK_PSK = 1), the phase of the carrier is shifted by 180 on any change of the DIO line. Here, the QSC transistor must be used. Figure 9. Modulation Modes
D_IO
Coil Voltage (ASK Mode)
Coil Voltage (PSK Mode) Switch Off Cycle
Modulation after Setup
Standby
The IC switches from modulation mode to command mode if the DIO-line has not been changed for a time peraiod longer than tmodsel.
QSC Feature
The Quick Start Control (QSC) feature supports a short oscillation build up and decay timing during LF data modulation. An external high-voltage MOS transistor is used as a switch to close and open the current loop of the antenna. By synchronizing this switch to the zero-crossing events of the antenna current, very short build-up and decay times for the LF-field and hence high data baud rates can be achieved. Figure 10. QSC Operation
DIO
QSC
Coil with QSC transistor ASK Modulation PSK Modulation
The external transistor (T1 in the typical applications section) is driven by the QSC pin. It provides a fast and synchronized gate-driver signal.
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Coil Driver
The coil driver is composed of a power MOS stage in half-bridge configuration, which is supplied by a current regulated boost converter. The driver generates a square-wave output signal to supply the antenna circuit with the carrier frequency. The antenna coil current is regulated by the voltage of the switch mode power supply. The current is therefore sensed by a shunt resistor connected between the VSHUNT and the GND pins of the IC. To avoid damages in case of short circuits and high currents, the driver is switched off by the integrated fault detection unit.
Current Adjustment
To provide an adjustable coil current, the IC is equipped with a voltage regulator composed of a Switch Mode Power Supply (SMPS), which is used if the supply voltage is too low to reach the desired antenna coil current. In this case, the driver stage voltage is brought up to the required level (maximum 40 V). The IC contains the control logic and the switching transistor for the boost converter. All other components like the choke coil and the capacitor have to be applied externally. The antenna coil current can be adjusted in 16 steps by modifying the I_Coil0 to I_Coil3 bits in the control register. According to the selected current, the pulse width of the antenna coil driver signal is adjusted in order to enlarge the control range for the voltage regulator. The 16 steps are scaled logarithmically and have the follwing current ratings: Table 9. Current Settings
Step 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Note:
(1)
Current [mA] Imaximum/3.158 Imaximum/2.927 Imaximum/2.727 Imaximum/2.5 Imaximum/2.353 Imaximum/2.143 Imaximum/2 Imaximum/1.846 Imaximum/1.714 Imaximum/1.579 Imaximum/1.463 Imaximum/1.367 Imaximum/1.263 Imaximum/1.165 Imaximum/1.081 Imaximum
I_Coil0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
I_Coil1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
I_Coil2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
I_Coil3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
P/P Ratio 1/7 1/7 1/7 1/7 2/6 2/6 2/6 2/6 3/5 3/5 3/5 3/5 4/4 4/4 4/4 4/4
1. Default
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ATA5277 [Preliminary]
The maximum output current can be selected with the external shunt resistor. Its resistance can be calculated with the formula: 1 R shunt = --------------------- W I max,peak where the minimum and maximum ratings for Imaximum,peak quoted in the DC characteristics have to be considered. See Figure 11 to determine the antennas parameters. The maximum reachable output current can be calculated as follows: V DRV 2 I ant,peak = ----------------------- A p Z Here, VDRV is the maximum reachable driver voltage (40 V) and Z the antennas impedance (inculding the RDSon of the QSC MOSFET, the shunt resistor and the driver output resistance).
Fault Diagnotics
The IC contains several fault diagnotic stages to protect itself from destruction and to provide diagnostic information. Once there is a fault detected, both the switch mode power supply and the antenna driver stage are switched off and the corresponding fault information is written into the status register. Note that besides shutting down the driver stages, the ATA5277 will not change its behaviour (i.e., it will remain in modulation mode until the DIO line timeout has occured). The fault information can be read out from status command 4, which will also reset the status register. Following protection and diagnostic mechanisms are defined: * General - * The IC is equipped with temperature measurement obilities in order to detect a critical junction temperature Short-circuit protection of the driver stage output is realized by means of voltage monitoring. Thus, the output voltage is compared to a corresponding threshold (depeding on the active transistor in the power MOS half-bridge). If this threshold is surpassed for several oscillations, a Short Circuit (SC) fault is detected; Open load or QSC transistor SC to GND is detected with the external current sensing resistor RShunt. If there is no signal at this point even if the output is active, there is at least one of those two faults present. There is no possibility to determine the exact fault source.
DRV output -
-
The diagnostic bits contain the information as given in Table 10 on page 14.
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Table 10. Diagnostic Bits
DIAG0 0 1 0 1 0 1 0 1 DIAG1 0 0 1 1 0 0 1 1 DIAG2 0 0 0 0 1 1 1 1 Fault Type No fault detected Open load or QSC transistor SC to GND Overtemperature Antenna driver SC to GND Antenna driver SC to VBATT QSC transistor SC to VBATT Not defined Not defined
Switch Inputs
The switch inputs SW1 and SW2 can be used to connect switches, e.g., the door handle contactors. These inputs are equipped with pull-ups, capable of driving currents up to 20 mA per pin. The pull-up voltage can be selected with the VSW input pin, which has to be connected either to VDD (5 V) for 5 V operation or to VBATT for 12 V operation. The state of the switches is determined by the voltage level at the corresponding pin. This information can be read out via the DIO-line during the status command 3. If the IC is in the standby mode, it wakes up if an input is pulled to ground. After a debounce time the IC generates a low signal at the DIO-line (wake-up). This signal can be used to wake up and request a microcontroller to read the switches with a setup cycle. Once the IC has woken up or during normal operation mode, a low state at a switch input (i.e., the switch is triggered) is stored until the status command 3 has been read out or ALYA enters standby mode. This enables the microcontroller to determine which of the two switch inputs was triggered, independant of the time it needs for processing status command 3. To prevent high standby currents caused by a hanging door switch or a short-circuited line, the pull-ups can be disabled individually by setting the DIS_SW1 and the DIS_SW2 bits in the command register 2.
CLKO Output Pin
The clock output pin CLKO on the ATA5277 can be used to supply an onboard microcontroller with a clock signal (either 8 or 4 MHz). Due to this frequency and the 5-V output stage, this signal is not suited to supply any device beyond the PCB boundaries. This clock signal is directly derived from the clock source connected to the OSCI/OSCO pins of the ATA5277 and is available as long as ATA5277 is not in standby mode. The frequency can be selected with the PS_CLK bit of control command 2, which is '0' for full clock rate (typical 8 MHz) or '1' for the half clock rate (4 MHz).
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ATA5277 [Preliminary]
Application Hints
Figure 11. Antenna Coil Inductance versus Quality
0.0005 0.00045 0.0004 inductnce L[H] 0.00035 0.0003 0.00025 0.0002 0.00015 0.0001 4 6 8 10 12 14 quality Q 16 18 20 22
antenna ind.
Figure 11 shows the maximum usable antenna coil inductance in order to meet the requirements (maximum output voltage of 40 V square wave, output peak current of 1 A, maximum frequency deviation of antenna is 2.5%).
Absolute Maximum Ratings
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Parameters Supply voltage Input voltage Power dissipation (IC, QFN) Emission Minimum ESD protection (100 pF through 1.5 k) Junction temperature Storage temperature range Note: 1. Voltages are given relative to VSS. Symbol VBATT VIN Ptot EMI ESD TJ Tstg Value -0.3 to +44 VSS-0.3 VIN 44 2 250 2 (onboard pins) 4 (offboard pins) 150 -55 to +150 Unit V V W V/M kV C C
Thermal Resistance
Parameters Thermal resistance junction-case Thermal resistance junction-ambient (QFN28) Symbol RthJC RthJA Value 5 32 Unit K/W K/W
Operating Range
Parameters Power supply range Operating temperature range Symbol VBATT Tamb Value 7 to 16.5 -40 to +85 Unit V C
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Electrical Characteristics (1)
No. 1 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.10 1.11 1.12 2 2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9 2.10 2.11 2.12 2.13 2.14 2.15 2.16 Parameters Power Supply Operating voltage SMPS voltage range Switching frequency Current regulation set up time Supply current Standby current Power on reset VBATT OV discharger Internal 5 V supply Integrator current dVCP for high side Thermal shutdown temperature Serial Interface Data output current Output low level Input impedance Input low level Input high level Serial Interface baud rate Signal rise-time (L to H) Signal fall-time (H to L) Wake-up debounce time Wake-up impulse length Minimum synchronize time Maximum set-up time Data valid time for input Data valid time for output Recovery time Bit length 5 V VDIO VBATT 5 V VDIO VBATT IDIO = 20 mA 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 14 IDIO VLout Rin VLin VHin BdIF trise tfall tdeb twake tsync tsetup tdata,in tdata,out trecover tbit 140 140 20 200 160 0 0 550 20 20 50 50 0.7 VDIO 5 1 1 0.6 10 1.2 20 1.5 3.5 0.4 VDIO mA V MW V V kbit/s s s s s s s s s s s A A A A A D A A D D D D D D D D After fusing = 2 IREF Clamping VBOOST Temperature reference = VSCANI IC in standby, VBATT > 23 V VS = 7 V IC in standby, VBATT = 12 V 24 24 24 20 12 6 15 24 4 26, 27, 28 VBATT VVDS fSMPS treg ISUP ISTB VPOR IDIS VVDD ICINT dVCP Tjsd 4.7 18 7.7 155 4.2 7 (2) 16.5 2 fCF 1 1,5 3.5 TBD 4.7 9.5 5.3 22 8.9 16.5 (2) 40 V V kHz ms Aeff A V mA V A V C D D C D D A A A A A A B Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. 7 V < VBATT < 16.5 V; Tamb = 25C unless otherwise specified; all values refer to GND pins 2. 6 V possible with approximately 30% decrease of maximum output power; 28 V operation possible (jump start), but output current stability is not guranteed
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ATA5277 [Preliminary]
Electrical Characteristics (1) (Continued)
No. 3 3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 4 4.1 4.2 4.3 4.4 5 5.1 5.2 5.3 5.4 Parameters Driver Stage Coil driver output voltage Coil driver output current Coil driver resistance QSC driver output voltage QSC driver output current QSC driver output highside-impedance QSC driver output lowside-impedance Carrier frequency range LF data baud rate Output rise/fall time Output duty cycle Door Switch Inputs Trigger voltage level Output current (pull-up) Input debounce time Oscillator set-up time Oscillator Input frequency range CLKO-output frequency CLKO high level CLKO low level Ceramic resonator, crystal or external CLKO source SCANI change 17 17 17 17 fOSC fOUT VHCLKO VLCLKO 6.4 fOSC/2 4.4 4 10 fOSC 7.1 2.2 MHz MHz V V B A A A Dependent on ceramic resonator 5 V VSW VBATT 21, 23 21, 23 17 17 VSWtrig ISW tdeb toscon 8 20 2 500 0.4 VSW 40 V mA ms s A A A D Bi-phase/ Manchester Between 10% and 90% of driver supply Short-term loads Square wave Depends on antenna inductance 4 5 5 8 8 8 8 5 5 26, 27, 28 5 VVDS IDRV,peak RDRV VQSC IQSC RQSCh RQSCl fCF BdRF trf DCF 12.5 100 1 TBD 50 3 3 150 8 0.4 10 20 50 VBATT 40 1 V Apeak W V mA W W kHz kbit/s s % A D A A A A A D D A A Test Conditions Pin Symbol Min. Typ. Max. Unit Type*
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter Notes: 1. 7 V < VBATT < 16.5 V; Tamb = 25C unless otherwise specified; all values refer to GND pins 2. 6 V possible with approximately 30% decrease of maximum output power; 28 V operation possible (jump start), but output current stability is not guranteed
Soldering Recommendations
Parameters Maximum heating rate Peak temperature in preheat zone Duration of time above melting point of solder Peak reflow temperature Maximum cooling rate Symbol TD ZPH tMP TPeak TrPeak Value 1 to 3 100 to 140 10 min/75 max 220 to 225 2 to 4 Unit C/s C s C C/s
17
4669B-RKE-10/03
Figure 12. Application Circuit
PGND SW1 5V Supply Osc SW2 Switch Debounce and Wake-up
Magnetic LF Link
VDS
LA
VSHUNT
ATA5277 [Preliminary]
VBATT min. 7 V VL VDD VSW Boost converter control
VBATT
18
DRV1 Driver Driver Control Logic Serial interface and Status/control register VDIO DIO
ATA5277
LF Receiver
CLKO
Microcontroller
Data
Sensing AGND DGND TEST
4669B-RKE-10/03
ATA5277 [Preliminary]
Ordering Information
Extended Type Number ATA5277-PCQ Package QFN28 Remarks 7 mm 7 mm
Package Information
19
4669B-RKE-10/03
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4669B-RKE-10/03

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